Like the Channel F, the CPU in the Video Brain is a Fairchild F8, but clocked at 2MHz. Unlike the Channel F, the Video Brain has a 3853 Static Memory Interface that gives it a standard address bus. This means that it uses normal ROMs, instead of the F8 3851 Program Storage Units that are so difficult to dump.
Along with the 3850 CPU and 3853 SMI, the main board has 8 21L02 static RAM chips for 1 kilobyte of RAM. It also has 2 2K ROMs, and 2 custom VLSI ICs named UV-201 and UV-202. There is a 40-pin edge connector that the keyboard attaches to, and a 45-pin cartridge connector (although cartridges typically only use 24 of the pins).
One ROM (labelled RES1) is mapped to address range $0000-$07FF, but because the addresses aren't fully decoded, the contents also appear at $4000-$47FF, which is what the code references. Reset causes a jump to $0000, which is the beginning of this ROM. The other ROM (RES2) is mapped to $2000-$27FF. RAM is from $0C00-$0FFF. Carts start at $1000; some are 2K and some are 4K in size. Some of the 4K carts use one ROM, some use 2.
Most of the address decoding is done by TTL chips, but some is done by the VLSIs. The RAM chips hang off the VLSIs, so they must also bridge to the CPU data bus. I believe the VLSIs have registers in the $0800-$08FF range for setting up the video output. Update: I did a patent search for Umtech, the original company name, and found a couple of patents that appear to be applicable. They describe custom chips that a CPU can use to draw graphics, and many of the technical details line up with what I'm seeing in the BIOS and cart disassemblies.
At this point in the investigation, I think that there are lo-res and hi-res graphics modes. Hi-res is used to display text and lo-res is used for the color bars. Hi-res is 128 horizontal pixels by 49 vertical- this gives 7 rows of 16 7-pixel tall characters, as seen in the text editor. Each byte in RAM displays as 8 adjacent pixels on the screen, one bit per pixel. There are only 2 colors- foreground and background. The first byte to display is at $0C2F - these are the top left 8 pixels. Interestingly, the rows of characters are immediately adjacent in RAM- there are no gaps between rows as seen on the display. This means that the hardware must insert those; saving 192 bytes that would just be empty.
There are configuration bytes at the top of RAM: data is copied to memory starting at $0FB1, and if it is overwritten, the screen becomes corrupt.
Patent 4,232,374 describes "Segment Ordering for Television Receiver Control Unit" filed by Umtech in 1977 and granted in 1980. This document describes the VideoBrain grapics hardware. It is a sprite engine, capable of displaying 16 sprites simultaneously. The control registers are documented pretty thoroughly. The sprites are monochromatic, but each can be a different color. There is one bit each for RGB, and 2 bits of intensity info (but maybe only 2 intensity levels are usable). The registers allow for a sprite up to 248x256 pixels, positioned on a grid 256x512 pixels in size. Sprites can be displayed at twice their horizontal or vertical size. There are 2 "display lists" for setting the y position and drawing priority of the sprites. There is also a mode called "xcopy" that replicates the first byte of a sprite horizontally.
In addition to the sprite functions, the chips have a register containing the current y-position on the screen, and can support a light pen or optical gun through x and y "freeze" registers that store the x and y positions when an interrupt occurs. The backgound can also be set to one of 8 colors / 4 intensity levels, and there is a "final modifier" that is exclusive-ored with every pixel's RGB and intensity bits. There is a register that tells whether the odd or even field is currently being displayed.
In Text Editor mode, there are 9 sprites- 7 are the lines of text. In Color Bars mode, there are 16 sprites; one for each color bar.
Text strings in the ROMs are stored using the same hex code that the keyboard produces (not ASCII, not even in alphabetical order, but based off the keyboard rows and columns):
{space}I"U!Y÷TxR9E8W7Q%A.O#K)J(H/G-F6D5S4Z1P¢L$M:N,B=V+C3X2?0;{pi}'*
I modified the RES1 ROM image so that when the SPECIAL button is hit, all of memory is written out the accessory port one bit at a time, and burned this image into a 2732 EPROM. I entered some text in the text editor, set the date and time, and set the alarm, then dumped memory: hexdump1.bin. Then I hit the COLOR button to display the color bars, and dumped memory again: hexdump2.bin. The VLSI registers at $0800-$088F are readable, but might have been changing as I dumped the data.
I used a similar ROM image to dump the carts that I've been sent so far:
If you have any other cart, please consider sending it to me for dumping. I just need to plug it into the Video Brain for 5 minutes, and I can return it right away.
The cart pinout is as follows. Most carts only have pads 1-24, but a couple of 2-ROM carts don't have 23 and 24, but have 28.
1 ground 2 D2 3 D1 4 D0 5 A0 6 A1 7 A2 8 A3 9 A4 10 A5 11 A6 12 A7 13 +5V 14 A8 15 A9 16 _CS1 (used for 2-ROM carts) 17 A10 18 D7 19 D6 20 D5 21 D4 22 D3 23 A11 24 A12 25 26 27 RESET 28 _CS2 (used for 2-ROM carts) 29 30 31 32 33 34 35 36 37 38 A13 39 40 41 R/_W 42 +5V 43 44 ground 45 ground
I've built a multicart that has a large EPROM and some RAM. It is capable of holding 31 cartridges, plus a menu system.
I think all the carts have been dumped except APL/S, the programming cart. If you loan this one to be dumped, I'll send you a free multicart.
Kevtris has fully analyzed the system and implemented it on an FPGA.
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