PSU diagram from patent overlaid on picture
more F8 info
3850 CPU data sheet
3851/3856 PSU data sheet
3852/3853 memory interface data sheet
F8 Guide To Programming
F8 family datasheet
F8 chapter from uP book
Released under GPL - no commercial use allowed
Peter's F8 assembler/disassembler
VideoBrain Clock Signals: The 4MHz crystal, 2MHz XTALY input and the 2MHz CPU clock PHI Note the gaps in the XTALY and PHI signals. At first I thought this was a problem with the unit, but that's how the CPU gets halted so that the graphics chips can take over the bus. Every 48 clocks, the chips take over for 3 microseconds. My cart dumper generates continuous clocks, so this must be done in software - probably an interrupt that I disabled.
VideoBrain Clock and ROMCx Signals: The 2MHz XTALY input, the 2MHz CPU clock PHI, the instruction clock WRITE and the 5 ROMC signals You can see short and long instruction cycles, as clocked by WRITE. I guess the CPU doesn't mind the really long cycles when XTALY is inhibited. The 5 ROMC signals can be decoded into some of the 32 ROMC states shown in the datasheet. If I'd hooked up the other 8 probes to the databus, we could see the opcodes being fetched as well.
VideoBrain Clocks: The 2MHz CPU clock PHI, the 2MHz clock from UV202 and the clock inhibit signal. Looking at the schematics of the early production VideoBrain, PHI originally came from one of the custom chips, UV202. This picture shows that it is also a 2MHz clock, but the CPU gets 50 clocks instead of 48. It would be interesting to know why they ditched the clock from UV202 and added hardware to generate it instead.
Grandstand Clock Signals: The 2MHz XTALY input, the 2MHz CPU clock PHI and the instruction clock WRITE
Grandstand Clock and ROMCx Signals: The 2MHz XTALY input, the 2MHz CPU clock PHI, the instruction clock WRITE and the 5 ROMC signals.
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