1000: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 

1012: 8f     DI   		;disable interrupts
1013: 31 00  SRP  #00h		;select register group 0
1015: b0 f6  CLR  P2M		;port 2 all out
1017: b0 f7  CLR  P3M		;port 3 
1019: b0 e4  CLR  R4		;starting address high
101b: b0 e5  CLR  R5		;starting address low
101d: 6c 10  LD   R6, #10h	;length high (4096)
101f: b0 e7  CLR  R7		;length low

1021: 2c 01  LD   R2, #01h	;dummy pattern for testing
1023: 2c 02  LD   R2, #02h
1025: 2c 04  LD   R2, #04h
1027: 2c 08  LD   R2, #08h
1029: 2c 10  LD   R2, #10h
102b: 2c 20  LD   R2, #20h
102d: 2c 40  LD   R2, #40h
102f: 2c 80  LD   R2, #80h
1031: 2c 55  LD   R2, #55h
1033: 2c aa  LD   R2, #AAh
1035: 2c ff  LD   R2, #FFh

1037: c2 84  LDC  R8, @RR4	;get byte at address
1039: 28 e8  LD   R2, R8	;output to port 2
103b: 3c 10  LD   R3, #10h	;set flag on port 3
103d: a0 e4  INCW R4		;next address
103f: b0 03  CLR  P3		;clear flag on port 3
1041: 80 e6  DECW R6		;decrement count
1043: eb f2  JR   NZ, 1037h	;loop until done

1045: 8b cb  JR   1012h		;start over

